1. Field of the Invention
The present invention relates to a semiconductor device and method for manufacture thereof, and more particularly to a semiconductor device and method for manufacture thereof wherein is checked the state of the formation of a P-channel barrier region or a guard ring region (these are integrated in these specifications and abbreviated as "channel barrier region") directly below a field oxide.
2. Description of the Related Art
A problem is the increase in passive current consumption because of cosmic rays (for example, g rays) when a trapping semiconductor device is used as a part of space instrumentation. This is because hole-electron pairs are generated in the field oxide by irradiation with g rays and so forth, then the holes, which have low mobility, are captured at the interface of the silicon substrate and oxidized silicon and a stationary positive charge is generated. In other words, the surface of the silicon substrate directly beneath the field oxide of a parasitic NMOS transistor reverses (in effect, the threshold voltage becomes low) because of this stationary positive charge and leaked current flows and causes the passive current consumption to increase. In order to prevent this increase in leaked current, a high density, P-type channel barrier region must be established directly beneath the field oxide. Also, in order to prevent a drop in withstand voltage in this case, it is also provided that the P-type channel barrier region be formed so as to be separated from the N-type diffusion layers such as the N-type source and drain regions.
For example, the technology for forming the aforementioned high density P-type channel barrier region so as to be separated from N-type diffusion layers is disclosed in Japanese Patent Laid-open Publication No. 2-304949, where P-type impurities are diffused in the substrate before the formation of a thick field oxide, and in Japanese Patent Laid-open Publication No. 6-140502, where P-type impurities are implanted in the substrate through the field oxide with high energy after the formation of a thick field oxide.
In either case, it is necessary to check the construction of the P-type channel barrier region, specifically the separation of the elements, and check elements are installed for this purpose. The conventional check elements are explained with reference to FIG. 13. In FIG. 13, (A) is a planar view and (B) is a sectional view of (A) at the line W-W'.
A field oxide 51 is formed on the P-type semiconductor substrate 50; N-type diffusion layers 63S, 63D are formed on either side of the location 51G on this field oxide 51. Directly below this field oxide 51G, a P-type channel barrier region 62 is formed so as to be separate from the N-type diffusion layer 63S, 63D, in order to improve element separation, and a thin oxide film 64 is formed thereon. Also, a polysilicon electrode 66 is formed above the field oxide 51G and extends over the thin oxide film 64. Aluminum electrodes 67S, 67D are each drawn through contact holes 68, which pass through the thin oxide film 64 from the BPSG film 52, which is an interlayer insulating film applied over the entirety, and extend to the N-type diffusion layers 63S, 63D. An aluminum electrode 67G is drawn through a through hole 65 which passes through the BPSG film 52 and extends to the polysilicon electrode 66.
Being the check elements in FIG. 13, the P-type channel barrier region 62, N-type diffusion layers 63S, 63D, thin oxide film 64, polysilicon electrode 66, and aluminum electrodes 67S, 67D, 67G are formed at the same time as the P-type channel barrier region, N-type source and drain regions, gate oxide, polysilicon gate electrode, and aluminum electrode of an insulated gate field effect transistor (abbreviated below as "MOS transistor"), which are circuit elements in the circuit element region established on the same substrate. The field oxide 51, 51G and interlayer insulating film 52, which are check elements in FIG. 13, are formed at the same time as the field oxide and interlayer insulating film in the circuit element region.
The parasitic MOS transistor structure is formed with these check elements: the N-type diffusion layer 63S becomes the N-type source region, the N-type diffusion layer 63D becomes the N-type drain region, the polysilicon electrode 66 becomes the gate electrode, and the field oxide 51G becomes the gate insulating film. Then a probe is brought into contact therewith and the size of the aluminum electrodes 67S, 67D, 67G, for measuring this parasitic MOS transistor, is 100 .mu.m square (area 1.times.10.sup.4 .mu.m.sup.2), determined according to the probing precision of the measurement device. Generally the following measurements are performed to evaluate element separation using these elements. In other words, 5 V is applied to the drain region 63D and 0 V (ground potential) is applied to the source region 63S and substrate 50; the gate voltage applied to the gate electrode 66 is gradually increased, and the gate voltage, at which the drain current becomes a certain value (1 .mu.A), is found. This gate voltage is called the threshold voltage of the parasitic MOS transistor; a higher value of this voltage indicates that element separation is higher.
The threshold voltage of this parasitic MOS transistor becomes 35 V for a film thickness of 450 nm of the field oxide 51G formed by the selective thermal oxidation method, called the LOCOS method, and especially when element separation is not improved. The threshold voltage of this parasitic MOS transistor becomes 40 V or more when a high density P-type channel barrier region 62 is established and element separation is improved.
As discussed above, the state of element separation in a semiconductor device was previously checked using the check elements shown in FIG. 13.
However, this prior art has the following problems.
The polysilicon electrode 66 and N-type diffusion layers 63S, 63D in FIG. 13 are placed on top of each other with the thin oxide film 64, which acts as the gate oxide, a circuit element, therebetween. In this section, the insulator is destroyed when a voltage greater than or equal to the true breakdown field (generally 10 MV/cm) of this thin oxide film 64 is applied. Recent gate oxide thicknesses have been 20 nm; therefore, the film thickness of the thin oxide film 64 has also been 20 nm. The oxide 64 in this section is destroyed when the gate voltage exceeds 20 V.
Additionally, the threshold voltage of the parasitic MOS transistor becomes 40 V or more when the P-type channel barrier region is established and element separation improved. Therefore it becomes impossible to evaluate the state of this P-type channel barrier region.
It is necessary to make a high density P-type channel barrier in order to prevent an increase in current leakage due to the stationary positive charge generated in this field oxide. In order to monitor the state of this density, the threshold voltage of the aforementioned parasitic MOS transistor is measured. However, the value of this threshold voltage is easily influenced by variations in thickness of the field oxide and a sensitive check of element separation according to the density of the P-type channel barrier is not possible.
Furthermore, three aluminum electrodes 67S, 67D, 67G are required in order to evaluate this, as shown in FIG. 13. Because the size of one of the aluminum electrodes is 100 .mu.m square as discussed above, a minimum area of 3.times.10.sup.4 .mu.m.sup.2 is required to form an aluminum electrode pattern comprising these three aluminum electrodes. Check elements requiring a large area as shown in FIG. 13 are not desirable because the area used by the original circuit element region should be increased and the area occupied by the check elements be made as small as possible.
Furthermore, with the check elements in FIG. 13, the orientation and degree of misplacement between the N-type diffusion layers or field oxide and the P-type channel barrier region cannot be easily evaluated.